1. Field of the Invention
The present invention relates to a PDP (plasma display panel) energy recovery apparatus and method and a high speed addressing method using the same, and more particularly to a PDP energy recovery apparatus and method for controlling the time point of charging and discharging energy to the PDP optimally and a high speed addressing method using the same.
2. Description of the Background Art
In the PDP, when a ultraviolet ray generated in plasma discharging due to He—Ne gas or Ne—Xe gas excites a red, a green and a blue fluorescent material formed at barrier ribs in discharge cells separated by cross barrier ribs, a character or a graphic is displayed by a visible ray on the basis of the principle that a visible ray is generated and discharged when the excited fluorescent material is transited in a base state. The discharge cells are arranged in a matrix and the one cell becomes a pixel on a screen.
The PDP having the above-described structure does not need an electric gun like a cathode ray tube, so that it can implement a thin, light and large screen with high definition.
As the PDP has an electrode, a dielectric layer and a discharge gas and is operated by charging and discharging, it is functioned like a capacitor for charging electric charge. Thus, the PDP consumes much energy in charging and discharging, and the larger its size is, the more energy is consumed.
Therefore, when the PDP is operated, in order to effectively consume the energy, an energy recovery apparatus is used to recover the energy which has been supplied to the PDP and to supply the recovered energy back to the PDP. The PDP energy recovery apparatus has been used to be connected with a sustain electrode by using a sustain waveform inputted to the sustain electrode, and recently, it is used to be also connected with a data electrode.
FIG. 1 is a perspective view showing a face-discharge type PDP structure in accordance with a conventional art.
As shown in the drawing, the conventional face-discharge type PDP includes an upper substrate 10, an scan/sustain electrode 12Y and a common/sustain electrode 12Z formed at the upper substrate 10, an upper dielectric layer 14 for accumulating a wall charge generated when plasma is discharged, a protective film 16 for preventing the upper dielectric layer 14 from damaging by sputtering generated when the plasma is discharged as well as heightening discharges of secondary electrons, a lower substrate 18, an address electrode 20X formed at the lower substrate 18, a lower dielectric layer 22 for accumulating a charge of the address electrode 20X, barrier ribs 24 formed at the lower dielectric layer 22 and a fluorescent material 26 coated on the barrier ribs 24 and at the lower dielectric layer 22.
The address electrode 20X is formed in a cross direction to the scan/sustain electrode 12Y and the common/sustain electrode 12Z, and the barrier rib 24 is formed in parallel with the address electrode 20X, so that the ultraviolet ray and the visible ray generated by discharging is not leaked to the adjacent discharge cell.
The fluorescent material 26 generates one of the red, the green and the blue visible rays excited by the ultraviolet rays generated when the plasma is discharged. An inert gas, such as He—Ne or Ne—Xe, is injected in the barrier ribs 24 formed between the upper substrate 10 and the lower substrate 18, for gas discharging.
Also, the protective film 16 is made of a material such as magnesium oxide (MgO).
FIG. 2 illustrates a construction of a drive unit of a AC face discharge type PDP in accordance with the conventional art, which includes a PDP 30 at which the scan/sustain electrode lines (Y1, Y2, . . . , Ym), the common/sustain electrode lines Z1, Z2, . . . , Zm) and address electrodes (X1, X2, . . . , Xn) are connected to form the discharge cells 1 arranged in a m×n matrix form, a scan/sustain driving unit 32 for driving the scan/sustain electrode lines, a common/sustain driving unit 34 for driving the common/sustain electrode lines, a first address electrode line driving unit 36A for driving the address electrode lines at odd numbers (X1, X3, . . . , Xn−1), and a second address electrode line driving unit 36B for driving and address electrode lines at even numbers (X2, X4, . . . , Xn). The scan/sustain driving unit 32 sequentially provides a scan pulse and a sustain pulse to the scan/sustain electrode lines to sequentially scan the discharge cells by lines and sustains discharging of m×n number of discharge cells.
The common/sustain driving unit 34 provides the sustain pulse to every common/sustain electrode lines, and the first and the second address driving units 36A and 36B provide an image data to the address electrode lines so as to be synchronized with the scan pulse. Subsequently, the first address driving unit 36A provides the image data to the odd number address electrodes X1, X3, . . . , Xn−1, while the second address driving unit 36B provides the image data to the even number address electrode lines X2, X4, . . . , Xn.
In order to discharge the AC face discharge type PDP by the address electrode and the sustain electrode, a voltage higher than hundreds of voltage must be supplied to the electrodes.
An energy recovery apparatus is installed at the scan/sustain driving unit, the common/sustain driving unit and the address driving unit to supply required energy to the address discharge and the sustain discharge according to the next data signal and minimize the energy to be supplied back to the address electrode and the sustain electrode according to the next data. That is, the energy recovery apparatus recovers the voltage charged at the scan/sustain electrode line (Y) and the common/sustain electrode line (Z) and the energy charged between the address electrode lines (X) and reuse the recovered energy as a driving voltage when the PDP is discharged again.
FIG. 3 is a circuit diagram of a PDP energy recovery apparatus in accordance with a first embodiment of the conventional art.
The PDP energy recovery apparatus includes a panel capacitor Cp installed connected with the scan/sustain driving unit 32, which is an equivalent circuit element to the PDP, and a PDP energy recovery circuit unit 38 for recovering energy of the panel capacitor Cp.
The PDP energy recovery circuit unit 38 includes an energy recovery capacitor Cr for charging and discharging the energy from and to the panel capacitor Cp, a coil L connected between the energy recovery capacitor Cr and the panel capacitor Cp so as to be make a resonance with the panel capacitor Cp, a first and a third switches S1 and S3 for switching the charge and discharge of the energy recovery capacitor Cr, a second switch S2 for switching supply of the power source (i.e., the sustain voltage) to the panel capacitor Cp, and a fourth switch S4 for grounding the panel capacitor Cp to lower a voltage level to the ground voltage when the panel capacitor Cp is discharged.
When the panel capacitor Cp discharges the sustain voltage Vsus, the voltage charged in the panel capacitor Cp is recovered and charged in the energy recovery capacitor Cr, and the charged voltage is discharged again to the panel capacitor Cp. In addition, the voltage (Vsus/2) corresponding to half of the sustain voltage of the panel capacitor Cp is charged in the energy recovery capacitor Cr.
The coil L forms a resonance circuit together with the panel capacitor Cp according to an operation of the first through the fourth switches.
The PDP energy recovery circuit unit 38 connected with the scan/sustain driving unit 32 may be also installed at the common/sustain driving unit 34.
The operation of the PDP energy recovery apparatus in accordance with the first embodiment of the present invention will now be described.
FIG. 4A is a waveform of an operation of the PDP energy recovery apparatus in accordance with the first embodiment of the conventional art.
Let's assume that, before a ‘T1’ interval, a voltage charged between the scan/sustain electrode line ‘Y’ and the common/sustain electrode line ‘Z’, that is, the voltage (VCp) charged in the panel capacitor Cp is ‘0’ and the half (Vsus/2) of the sustain voltage is to be charged in the energy recovery capacitor Cr.
At T1 interval, when the first switch S1 is turned on, a current path is formed from the energy recovery capacitor Cr through the first switch S1, the coil L to the panel capacitor Cp, so that the voltage Vsus/2 charged in the energy recovery capacitor Cr flows to the panel capacitor Cp.
At this time, since the coil L and the panel capacitor Cp forms a serial resonance circuit, as the voltage Vsus/2 charged in the energy recovery capacitor Cr passes the coil L of the serial resonance circuit.
At a T2 interval, since the first switch S1 is turned off in a state that the second switch S2 is turned on, the sustain voltage is supplied to the scan/sustain electrode line ‘Y’, so that the voltage of the panel capacitor sustains the sustain voltage Vsus.
At a T3 interval, when the second switch S2 is turned off and the third switch S3 is turned on, the sustain voltage Vsus charged in the panel capacitor Cp is discharged to the energy recovery capacitor Cr through the coil L and the third switch S3. As the panel capacitor Cp is discharged, the sustain voltage Vsus charged in the panel capacitor drops, and at the same time, the voltage of Vsus/2 is charged in the energy recovery capacitor Cr.
At a T4 interval, when the third switch S3 is turned off and the fourth switch S4 is turned on, since the voltage level of the panel capacitor Cp is grounded (GND), the voltage VCp of the panel capacitor Cp becomes ‘0’.
At a T5 interval, the state of the T4 interval is maintained for a certain time.
Accordingly, as the AC pulse is supplied to the scan/sustain electrode line ‘Y’ and the common/sustain electrode line ‘Z’ during the T1˜T5 intervals, the voltage VCP is repeatedly charged in and discharged from the panel capacitor Cp.
In this respect, the current iL flows to the coil as a resonance current when the panel capacitor Cp is charged and discharged.
FIG. 5A is a PDP energy recovery apparatus in accordance with a second embodiment of the conventional art.
As shown in the drawing, the PDP energy recovery apparatus includes a panel capacitor Cp as an equivalent circuit element to the PDP, an address driving unit 36A for controlling driving of the PDP, and a PDP energy recovery circuit unit 40 for recovering the energy of the panel capacitor Cp.
The address driving unit 36A implemented as an integrated circuit includes a logic processor 36A-1 for processing a small signal, FETs Q1 and Q2 for receiving the output signals of the logic processor 36A-1 to their gates and switching data signals according to the output signal, and a high voltage processor 36A-2 having parasitic diodes D1 and D2 respectively connected to the FETs Q1 and Q2.
The PDP energy recovery circuit unit 40 includes an energy recovery capacitor Cr for charging and discharging energy from and to the panel capacitor Cp, a coil L connected between the energy recovery capacitor Cr and the panel capacitor Cp to make a resonance with the panel capacitor Cp, a first and a third switches S1 and S3 for switching charge and discharge of the energy recovery capacitor Cr, a second switch S2 for switching supply of a power Vd to the panel capacitor Cp, and a fourth switch S4 for grounding the panel capacitor Cp to lower down a voltage level of the panel capacitor Cp to a ground voltage when the panel capacitor Cp is discharged.
The operation of the PDP energy recovery apparatus of the second embodiment of the present invention constructed as described will now be explained.
When the energy recovery apparatus is operated and the PDP is successively charged and discharged, the second switch S2 and the fourth switch S4 are switched in balance to supply and recover the energy, so that the energy recovery capacitor Cr included in the PDP energy recovery unit 40 is charged with the half voltage Vsus/2 of the voltage charged in the PDP. That is, when the third switch S3 is turned on, the half voltage Vsus/2 of the voltage which has been supplied to the data electrode is charged in the energy recovery capacitor Cr, and then, the fourth switch S4 is turned on to ground the voltage level of the panel capacitor Cp.
Only when a data is supplied, the driver IC 36A receives the Vsus/2 voltage from the PDP energy recovery circuit unit 40 and supplies it to the panel capacitor Cp. And then, the driver IC 36A switches on or off according to a scanning time so that the voltage charged in the panel capacitor Cp is charged in the energy recovery capacitor Cr.
At a T1 interval, when the first FET Q1 receives a high level signal from the logic processing unit 36A-1 and is turned on, it receives the Vsus voltage from the PDP energy recovery circuit unit 40, and at T2 interval, the 1 FET Q1 keeps turning on till the section where the high level data is maintained, so that the voltage is supplied from the energy recovery unit 40 thereto.
At a T3 interval, when the data is changed from a high level to a low level, the energy supplied to the data electrode is recovered from the PDP energy recovery circuit 40 through the first FET Q1 and the parasitic diode D1.
The T1 interval is an energy recovery ascending interval, that is, energy up (Er_up) corresponding to the state that the first switch S1 of the PDP energy recovery circuit unit 40 is turned on, and the T2 interval is an energy up sustaining interval (Sus_up) corresponding the state that the second switch S2 is turned on.
The T3 and T4 intervals are an energy recovery down intervals corresponding to the states that the third switch S3 is turned on, and the T5 interval is an energy down sustaining interval (Sus_down) corresponding to the state that the fourth switch S4 is turned on.
In the output wave form of the panel capacitor Cp, the T2 interval is an interval to transmit the data voltage, and the other intervals are operation intervals for supplying and recovering energy to effectively supply the data voltage.
Accordingly, in order to address the data at a high speed, the time for the intervals except for the T2 interval should be short.
FIG. 5B is an equivalent circuit diagram of the PDP energy recovery apparatus, which includes a fifth switch S5 and a sixth switch S6 equivalent to the logic processing unit 36A-1, the FETs and the parasitic diode, D1 and D2, included in the address driving unit 36A of FIG. 5A.
Meanwhile, like the first address driving unit 36A, the second address driving unit 36B may be installed to be connected with the PDP energy recovery circuit unit 40, based on which the operation of the PDP energy recovery apparatus in accordance with the second embodiment of the conventional will now be described.
FIG. 6 illustrates operational wave forms of the PDP energy recovery apparatus of FIG. 5A or FIG. 5B in accordance with the second embodiment of the conventional art.
Let's assume that, before the T1 interval, a voltage charged between the address electrode lines (X), that is, the voltage charged in the panel capacitor Cp, is ‘0’ and Vd/2 voltage is charged in the energy recovery capacitor Cr is charged.
At a T1 interval, if the first and the fifth switches S1 and S5 are turned on (At this time, if the discharge cell of the PDP is not selected, that is, no data pulse is supplied to the address electrode line ‘X’, the fifth switch S5 is maintained to be turned off), a current path is formed from the energy recovery capacitor Cr to the first switch S1, the coil L and to the panel capacitor Cp.
Since the coil L and the panel capacitor Cp form a serial resonance circuit, the voltage VCp of the panel capacitor Cp goes up to Vd which is twice of the voltage Vd/2 of the energy recovery capacitor.
At a T2 interval, since the first switch S1 is turned off in the state that the second switch S2 is turned on, the address voltage Vd is supplied to the address electrode line ‘X’, so that the voltage VCp of the panel capacitor Cp sustains the address voltage Vd.
At a T3 interval, when the second switch S2 is turned off and the third switch S3 is turned on, the address voltage Vd charged in the panel capacitor Cp is discharged through the coil L and the third switch S3 to the energy recovery capacitor.
When the panel capacitor Cp is discharged, the address voltage Vd charged in the panel capacitor Cp goes down, and at the same time, the voltage Vd/2 is charged in the energy recovery capacitor Cr.
At a T4 interval, when the third switch S3 is turned off and the fourth and the fifth switches S4 and S5 are turned on, the voltage level of the panel capacitor Cp is grounded (GND) and the voltage VCp of the panel capacitor Cp becomes ‘0’.
At a T5 interval, the voltage state of the T4 is maintained for a predetermined time.
Accordingly, the AC pulse is supplied to the address electrode line ‘X’ at the T1˜T5 intervals, so that the voltage VCP is repeatedly charged in and discharged from the panel capacitor Cp.
The current iL flows to the coil as a resonance current when the panel capacitor Cp is charged and discharged.
The output wave form of the panel capacitor Cp will now be described in detail.
FIGS. 7A through 7D are wave forms of the T1˜T5 intervals of FIG. 6.
At the T1 interval, as shown in FIG. 7A, when the first and the fifth switches S1 and S5 are turned on, a resonance circuit is formed by the coil L and the panel capacitor Cp, generating a resonance wave form.
At this time, the panel capacitor Cp is charged at the first resonance point 42 of a resonance wave form. When the second switch S2 is turned on, an output wave form of the panel capacitor is generated next the first resonance point 42 as shown in FIG. 7B.
At the T3 and T4 intervals, as shown in FIG. 7C, when the third switch S3 is turned on, a resonance circuit is formed by the coil L and the energy recovery capacitor Cr, generating a resonance wave form. At this time, the energy recovery capacitor Cr is charged when the resonance wave form goes down to the second resonance point 44.
After the resonance wave form goes down to the second resonance point 44, when the fourth switch S4 is turned on, as shown in FIG. 7D, an output wave form of the panel capacitor Cp is generated.
Accordingly, a data pulse is generated through the processes of FIGS. 7A˜7D.
FIG. 8 illustrate a wave form showing a data pulse of the PDP energy recovery apparatus in accordance with the conventional art.
The data pulse outputted according to the operation of the PEP energy recovery apparatus of the conventional art is divided into a P1 interval (corresponding to the T1 interval of FIGS. 4 and 6) where a voltage is charged in the panel capacitor Cp, a P2 interval (corresponding to the T2 interval of FIGS. 4 and 6) where the data pulse is supplied to the address electrode line, a P 3 interval (corresponding to the T3 and T4 intervals of FIGS. 4 and 6) where the voltage charged in the panel capacitor is recovered to be charged in a source capacitor, and a P4 interval (corresponding to T5 interval of FIGS. 4 and 6) where the voltage of the panel capacitor Cp goes down to ‘0’.
The P2 interval is substantially required for address discharge, while the P1, P3 and P4 intervals are preliminary intervals at which the voltage is charged in the energy recovery capacitor Cr and the panel capacitor Cp.
In this respect, the higher the addressing speed, the more increasing the ground level duration. That is, the P2 interval, which is substantially required for the address discharge, is reduced, whereas the intervals P1, P3 and P4 for charging the voltage to the energy recovery capacitor Cr and the panel capacitor Cp are not reduced.
Therefore, the preliminary intervals at which the voltage is charged in the energy recovery capacitor and the panel capacitor are not controllable, it is difficult to perform addressing at a high speed.
The conventional art is disadvantageous from the following reason. For example, when the AC face discharging PDP of the conventional art operates, an address interval (or an address discharge pulse width) should be more than 2.5 μs. In this respect, however, in a state that an interval of one frame is fixed by 16.7 ms, if the address discharge pulse width is lengthened to more than 2.5 μs, the rate that the sustain interval which substantially controls the brightness of a screen drops to below 30%.
In addition, in order to reduce the contour noise generated at the mobile image, sub-fields in one frame interval increase from 8 to 10˜12 in number.
Moreover, if the number of sub-fields is increased in the fixed one frame interval, each sub-field interval is accordingly shortened, and in this case, the address interval is fixed by sub-fields while only the sustain interval is shortened for a stable discharge.
Furthermore, if the scan/sustain electrode lines increase in number, the sustain interval at the high resolution PDP is too shortened, failing to display an image through the PDP.
Thus, in the high resolution PDP, the address interval that the scan/sustain electrode lines are sequentially driven is lengthened. Then, the sustain interval is shortened at the fixed one frame interval.
In addition, the energy recovery circuit of the conventional art is also disadvantageous in that in case that there is much change in the data supplied to the address electrode lines, the energy consumption can be reduced. But, in case of a full white data and a blank data with no data change, the energy is rather consumed due to the unnecessary switching operation in the energy recovery circuit. That is, in case of the full white data, the address data must be supplied to the every address electrode line.
In the case that the address data is supplied to the every address electrode line, the address driving unit should outputs a data pulse continuously.
However, even in this case, the energy recovery circuit should perform the unnecessary switching operation, much energy is consumed. Accordingly, in the conventional energy recovery apparatus, the energy recovery circuit is not operated in case of the full white data and the blank data upon checking the data. In this respect, however, since the PDP energy recovery circuit should be turned on and off only in case of the full white data and the blank data among the diversely changed data, the energy is unnecessarily consumed.
Moreover, in the conventional PDP every recovery apparatus, the energy recovery circuit used for data processing includes many switching units, and since the energy down sustain (Sus_down) operation, that is, a process for lowing down the level to a base voltage, is necessarily performed, the energy recovery apparatus has a large size and is not capable to addressing a data at a high speed.